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1 1605fc ltc1605 typical applicatio u descriptio u applicatio s u features 16-bit, 100ksps, sampling adc the ltc 1605 is a 100ksps, sampling 16-bit a/d con- verter that draws only 55mw (typical) from a single 5v supply. this easy-to-use device includes sample-and- hold, precision reference, switched capacitor successive approximation a/d and trimmed internal clock. the ltc1605? input range is an industry standard 10v. maximum dc specs include 2.0lsb inl and 16-bits no missing codes over temperature. an external reference can be used if greater accuracy over temperature is needed. the adc has a microprocessor compatible, 16-bit or two byte parallel output port. a convert start input and a data ready signal (busy) ease connections to fifos, dsps and microprocessors. single 5v supply bipolar input range: 10v power dissipation: 55mw typ guaranteed no missing codes sample rate: 100ksps integral nonlinearity: 2.0lsb max signal-to-noise ratio: 86db typ operates with internal or external reference internal synchronized clock improved 2nd source to ads7805 and ad976 28-pin 0.3?pdip, ssop and sw packages industrial process control multiplexed data acquisition systems high speed data acquisition for pcs digital signal processing low power, 100khz, 16-bit sampling adc on 5v supply 4k 20k 20k 200 ? reference 4k 10k 16-bit sampling adc d15 to d0 33.2k 2.2 f 10 f 0.1 f 2.2 f 10v input v in cap ref agnd1 1 4 3 2 agnd2 5 dgnd 14 control logic and timing busy byte cs r/c 28 27 6 to 13 15 to 22 26 25 24 23 digital control signals 1605 ?ta01 16-bit or 2 byte parallel bus 5v v dig v ana buffer typical inl curve code 0 inl (lsbs) 65535 1605 ? ta02 16384 32768 49152 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 , ltc and lt are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners.
2 ltc1605 1605fc a u g w a w u w a r b s o lu t exi t i s wu u package / o rder i for atio (notes 1, 2) v ana .......................................................................... 7v v dig to v ana ........................................................... 0.3v v dig ........................................................................... 7v ground voltage difference dgnd, agnd1 and agnd2 .............................. 0.3v analog inputs (note 3) v in ..................................................................... 25v cap ............................ v ana + 0.3v to agnd2 ?0.3v ref .................................... indefinite short to agnd2 momentary short to v ana digital input voltage (note 4) ........ dgnd ?0.3v to 10v digital output voltage ........ v dgnd ?0.3v to v dig + 0.3v power dissipation .............................................. 500mw operating ambient temperature range ltc1605c ............................................... 0 c to 70 c ltc1605i ............................................ 40 c to 85 c storage temperature range ................. 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c co n verter characteristics u ltc1605 ltc1605a parameter conditions min typ max min typ max units resolution 16 16 bits no missing codes 15 16 bits transition noise 1.0 1.0 lsb integral linearity error (note 7) 3 2lsb bipolar zero error ext. reference = 2.5v (note 8) 10 10 mv bipolar zero error drift 2 2 ppm/ c full-scale error drift 7 5 ppm/ c full-scale error ext. reference = 2.5v (notes 12, 13) 0.50 0.25 % full-scale error drift ext. reference = 2.5v 2 2 ppm/ c power supply sensitivity v ana = v dig = v dd v dd = 5v 5% (note 9) 8 8lsb the denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. with external reference (notes 5, 6). order options tape and reel: add #tr lead free: add #pbf lead free tape and reel: add #trpbf lead free part marking: http://www.linear.com/leadfree/ order part number consult ltc marketing for parts specified with wider operating temperature ranges. ltc1605acg ltc1605acsw ltc1605aig ltc1605aisw ltc1605cg t jmax = 125 c, ja = 95 c/w (g) t jmax = 125 c, ja = 130 c/w (n) t jmax = 125 c, ja = 130 c/w (sw) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 v in agnd1 ref cap agnd2 d15 (msb) d14 d13 d12 d11 d10 d9 d8 dgnd v dig v ana busy cs r/c byte d0 d1 d2 d3 d4 d5 d6 d7 g package 28-lead plastic ssop sw package 28-lead plastic so wide n package 28-lead pdip top view ltc1605cn ltc1605csw ltc1605ig ltc1605in ltc1605isw
3 1605fc ltc1605 ltc1605/ltc1605a parameter conditions min typ max units v ref output voltage i out = 0 2.470 2.500 2.520 v v ref output tempco i out = 0 5 ppm/ c internal reference source current 1 a external reference voltage for specified linearity (notes 9, 10) 2.30 2.50 2.70 v external reference current drain ext. reference = 2.5v (note 9) 100 a cap output voltage i out = 0 2.50 v ltc1605/ltc1605a symbol parameter conditions min typ max units s/(n + d) signal-to-(noise + distortion) ratio 1khz input signal (note 14) 87.5 db 10khz input signal 87 db 20khz, 60db input signal 30 db thd total harmonic distortion 1khz input signal, first 5 harmonics 102 db 10khz input signal, first 5 harmonics 94 db peak harmonic or spurious noise 1khz input signal 102 db 10khz input signal 94 db full-power bandwidth (note 15) 275 khz aperture delay 40 ns aperture jitter sufficient to meet ac specs transient response full-scale step (note 9) 2 s overvoltage recovery (note 16) 150 ns (notes 5, 14) the denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 5) ltc1605/ltc1605a symbol parameter conditions min typ max units v in analog input range (note 9) 4.75v v ana 5.25v, 4.75v v dig 5.25v 10 v c in analog input capacitance 10 pf r in analog input impedance 20 k ? a n alog i n put uu dy n a m ic accuracy u w i n ter n al refere n ce characteristics uu u digital i n puts a n d digital outputs uu the denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 5) the denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 5) ltc1605/ltc1605a symbol parameter conditions min typ max units v ih high level input voltage v dd = 5.25v 2.4 v v il low level input voltage v dd = 4.75v 0.8 v i in digital input current v in = 0v to v dd 10 a c in digital input capacitance 5pf v oh high level output voltage v dd = 4.75v i o = ?0 a 4.5 v i o = 200 a 4.0 v
4 ltc1605 1605fc ltc1605/ltc1605a symbol parameter conditions min typ max units v dd positive supply voltage (notes 9, 10) 4.75 5.25 v i dd positive supply current 11 16 ma p dis power dissipation 55 80 mw ltc1605/ltc1605a symbol parameter conditions min typ max units v ol low level output voltage v dd = 4.75v i o = 160 a 0.05 v i o = 1.6ma 0.10 0.4 v i oz hi-z output leakage d15 to d0 v out = 0v to v dd , cs high 10 a c oz hi-z output capacitance d15 to d0 cs high (note 9) 15 pf i source output source current v out = 0v ?0 ma i sink output sink current v out = v dd 10 ma digital i n puts a n d digital outputs uu ltc1605/ltc1605a symbol parameter conditions min typ max units f sample(max) maximum sampling frequency 100 khz t conv conversion time 8 s t acq acquisition time 2 s t 1 convert pulse width (note 11) 40 ns t 2 data valid delay after r/c (note 9) 8 s t 3 busy delay from r/c c l = 50pf 65 ns t 4 busy low 8 s t 5 busy delay after end of conversion 220 ns t 6 aperture delay 40 ns t 7 bus relinquish time 10 35 83 ns t 8 busy delay after data valid 50 200 ns t 9 previous data valid after r/c 7.4 s t 10 r/c to cs setup time (notes 9, 10) 10 ns t 11 time between conversions 10 s t 12 bus access and byte delay (notes 9, 10) 10 83 ns ti m i n g characteristics w u power require m e n ts w u note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to ground with dgnd, agnd1 and agnd2 wired together (unless otherwise noted). note 3: when these pin voltages are taken below ground or above v ana = v dig = v dd , they will be clamped by internal diodes. this product can handle input currents of greater than 100ma below ground or above v dd without latch-up. note 4: when these pin voltages are taken below ground, they will be clamped by internal diodes. this product can handle input currents of 90ma below ground without latchup. these pins are not clamped to v dd . note 5: v dd = 5v, f sample = 100khz, t r = t f = 5ns unless otherwise specified. note 6: linearity, offset and full-scale specifications apply for a v in input with respect to ground. note 7: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual end points of the transfer curve. the deviation is measured from the center of the quantization band. the denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 5) the denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 5) the denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 5)
5 1605fc ltc1605 electrical characteristics note 8: bipolar offset is the offset voltage measured from 0.5 lsb when the output code flickers between 0000 0000 0000 0000 and 1111 1111 1111 1111. note 9: guaranteed by design, not subject to test. note 10: recommended operating conditions. note 11: with cs low the falling r/c edge starts a conversion. if r/c returns high at a critical point during the conversion it can create small errors. for best results ensure that r/c returns high within 3 s after the start of the conversion. note 12: as measured with fixed resistors shown in figure 4. adjustable to zero with external potentiometer. note 13: full-scale error is the worst-case of ?s or +fs untrimmed deviation from ideal first and last code transitions, divided by the transition voltage (not divided by the full-scale range) and includes the effect of offset error. note 14: all specifications in db are referred to a full-scale 10v input. note 15: full-power bandwidth is defined as full-scale input frequency at which a signal-to-(noise + distortion) degrades to 60db or 10 bits of accuracy. note 16: recovers to specified performance after (2 ?fs) input overvoltage. typical perfor m a n ce characteristics u w supply current vs supply voltage change in cap voltage vs load current supply voltage (v) 4.50 9.5 supply current (ma) 10.0 10.5 11.0 11.5 12.0 12.5 4.75 5.00 5.25 5.50 1605 ?tpc01 f sample = 100khz load current (ma) ?5 change in cap voltage (mv) 10 30 50 15 1605 tpc03 ?0 ?0 0 20 40 ?0 ?0 ?0 ?5 ? 5 25 temperature ( c) ?0 10.0 positive supply current (ma) 10.5 11.0 11.5 12.0 25 0 25 50 1605 ?tpc02 75 100 f sample = 100khz supply current vs temperature typical inl curve code 0 inl (lsbs) 65535 1605 ?tpc04 16384 32768 49152 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 code 0 dnl (lsbs) 65535 1605 ?tpc05 16384 32768 49152 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 power supply feedthrough vs ripple frequency typical dnl curve ripple frequency (hz) ?0 ?0 ?0 ?0 ?0 ?0 power supply feedthrough (db) 1m 1605 ?tpc06 1 100 10 1k 100k 10k
6 ltc1605 1605fc typical perfor m a n ce characteristics u w ltc1605 nonaveraged 4096 point fft plot frequency (khz) 130 120 100 110 ?0 ?0 ?0 ?0 ?0 0 ?0 ?0 ?0 ?0 magnitude (db) 1605 ?tpc07 0 5 10 15 20 25 30 35 40 45 50 f sample = 100khz f in = 1khz sinad = 87.5db thd = ?01.7db sinad vs input frequency input frequency (khz) 1 sinad (db) 90 89 88 87 86 85 84 83 82 81 10 100 1605 ?tpc08 total harmonic distortion vs input frequency input frequency (khz) 1 total harmonic distortion (db) ?0 ?0 ?0 100 110 10 100 1605 ?tpc09 pi n fu n ctio n s uuu v in (pin 1): analog input. connect through a 200 ? resistor to the analog input. full-scale input range is 10v. agnd1 (pin 2): analog ground. tie to analog ground plane. ref (pin 3): 2.5v reference output. bypass with 2.2 f tantalum capacitor. can be driven with an external refer- ence. cap (pin 4): reference buffer output. bypass with 2.2 f tantalum capacitor. agnd2 (pin 5): analog ground. tie to analog ground plane. d15 to d8 (pins 6 to 13): three-state data outputs. hi-z state when cs is high or when r/c is low. dgnd (pin 14): digital ground. d7 to d0 (pins 15 to 22): three-state data outputs. hi-z state when cs is high or when r/c is low. byte (pin 23): byte select. with byte low, data will be output with pin 6 (d15) being the msb and pin 22 (d0) being the lsb. with byte high the upper eight bits and the lower eight bits will be switched. the msb is output
7 1605fc ltc1605 pi n fu n ctio n s uuu on pin 15 and bit 8 is output on pin 22. bit 7 is output on pin 6 and the lsb is output on pin 13. r/c (pin 24): read/convert input. with cs low, a falling edge on r/c puts the internal sample-and-hold into the hold state and starts a conversion. with cs low, a rising edge on r/c enables the output data bits. cs (pin 25): chip select. internally or? with r/c. with r/c low, a falling edge on cs will initiate a conversion. with r/c high, a falling edge on cs will enable the output data. busy (pin 26): output shows converter status. it is low when a conversion is in progress. data valid on the rising edge of busy. cs or r/c must be high when busy rises or another conversion will start without time for signal acquisition. v ana (pin 27): 5v analog supply. bypass to ground with a 0.1 f ceramic and a 10 f tantalum capacitor. v dig (pin 28): 5v digital supply. connect directly to pin 27. test circuits load circuit for access timing 1k c l c l dbn dbn 1k 5v ltc1605 ?tc01 a. hi-z to v oh and v ol to v oh b. hi-z to v ol and v oh to v ol load circuit for output float delay 1k 50pf 50pf dbn dbn 1k 5v ltc1605 ?tc02 a. v oh to hi-z b. v ol to hi-z fu n ctio n al block diagra uu w 16-bit capacitive dac comp ref buf 2.5v ref cap (2.5v) c sample c sample d15 d0 busy control logic r/c byte internal clock cs zeroing switches v dig v ana v in ref agnd1 agnd2 dgnd 16 ltc1605 ?bd + successive approximation register output latches 4k 20k 4k 10k
8 ltc1605 1605fc applicatio n s i n for m atio n wu u u driving the analog inputs the nominal input range for the ltc1605 is 10v or ( 4 ?v ref ) and the input is overvoltage protected to 25v. the input impedance is typically 20k ? , therefore, it should be driven with a low impedance source. wideband noise coupling into the input can be minimized by placing a 1000pf capacitor at the input as shown in figure 2. an npo-type capacitor gives the lowest distortion. place the capacitor as close to the device input pin as possible. if an amplifier is to be used to drive the input, care should be taken to select an amplifier with adequate accuracy, linear- ity and noise for the application. the following list is a summary of the op amps that are suitable for driving the ltc1605. more detailed information is available in the linear technology data books and linearview tm cd-rom. conversion details the ltc1605 uses a successive approximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a 16-bit or two byte parallel output. the adc is complete with a precision reference and an internal clock. the control logic provides easy interface to micro- processors and dsps. (please refer to the digital interface section for the data format.) conversion start is controlled by the cs and r/c inputs. at the start of conversion the successive approximation register (sar) is reset. once a conversion cycle has begun it cannot be restarted. during the conversion, the internal 16-bit capacitive dac output is sequenced by the sar from the most significant bit (msb) to the least significant bit (lsb). referring to figure 1, v in is connected through the resistor divider to the sample-and-hold capacitor during the acquire phase and the comparator offset is nulled by the autozero switches. in this acquire phase, a minimum delay of 2 s will provide enough time for the sample-and-hold capacitor to acquire the analog signal. during the convert phase, the autozero switches open, putting the comparator into the compare mode. the input switch switches c sample to ground, injecting the analog input charge onto the summing junc- tion. this input charge is successively compared with the binary-weighted charges supplied by the capacitive dac. bit decisions are made by the high speed comparator. at the end of a conversion, the dac output balances the v in input charge. the sar contents (a 16-bit data word) that represents the v in are loaded into the 16-bit output latches. figure 1. ltc1605 simplified equivalent circuit v dac 1605 ?f01 + c dac dac sample hold c sample s a r 16-bit latch comparator sample si r in2 r in1 v in 1605 ?f02 1000pf 33.2k v in cap a in 200 ? figure 2. analog input filtering lt1007 - low noise precision amplifier. 2.7ma supply current 5v to 15v supplies. gain bandwidth product 8mhz. dc applications. lt1097 - low cost, low power precision amplifier. 300 a supply current. 5v to 15v supplies. gain bandwidth product 0.7mhz. dc applications. lt1227 - 140mhz video current feedback amplifier. 10ma supply current. 5v to 15v supplies. low noise and low distortion. lt1360 - 37mhz voltage feedback amplifier. 3.8ma sup- ply current. 5v to 15v supplies. good ac/dc specs. lt1363 - 50mhz voltage feedback amplifier. 6.3ma sup- ply current. good ac/dc specs. lt1364/lt1365 - dual and quad 50mhz voltage feedback amplifiers. 6.3ma supply current per amplifier. good ac/ dc specs. linearview is a trademark of linear technology corporation
9 1605fc ltc1605 applicatio n s i n for m atio n wu u u internal voltage reference the ltc1605 has an on-chip, temperature compensated, curvature corrected, bandgap reference, which is factory trimmed to 2.50v. the full-scale range of the adc is equal to ( 4 ?v ref ) or nominally 10v. the output of the reference is connected to the input of a unity-gain buffer through a 4k resistor (see figure 3). the input to the buffer or the output of the reference is available at ref (pin 3). the internal reference can be overdriven with an external reference if more accuracy is needed. the buffer output drives the internal dac and is available at cap (pin 4). the cap pin can be used to drive a steady dc load of less than 2ma. driving an ac load is not recommended because it can cause the performance of the converter to degrade. figure 3. internal or external reference source s s + 1605 ?f03 internal capacitor dac bandgap reference v ana 4k 2.2 f cap (2.5v) 2.2 f ref (2.5v) 4 3 for minimum code transition noise the ref pin and the cap pin should each be decoupled with a capacitor to filter wideband noise from the reference and the buffer (2.2 f tantalum). offset and gain adjustments the ltc1605 offset and full-scale errors have been trimmed at the factory with the external resistors shown in figure 4. this allows for external adjustment of offset and full scale in applications where absolute accuracy is important. see figure 5 for the offset and gain trim circuit. first adjust the offset to zero by adjusting resistor r3. apply an input voltage of ?52.6mv ( 0.5lsb) and adjust r3 so the code is changing between 1111 1111 1111 1111 and 0000 0000 0000 0000. the gain error is trimmed by adjusting resistor r4. an input voltage of 9.999542v (+fs ?1.5lsb) is applied to v in and r4 is adjusted until the output code is changing between 0111 1111 1111 1110 and 0111 1111 1111 1111. figure 6 shows the bipolar transfer character- istic of the ltc1605. figure 4. 10v input without trim + 5 4 3 2 1 2.2 f + 2.2 f 33.2k 1% 10v input 200 ? 1% v in agnd1 ref cap agnd2 ltc1605 1605 ?f04 figure 5. 10v input with offset and gain trim input voltage (v) 0v output code ? lsb 1605 ?f06 011...111 011...110 000...001 000...000 100...000 100...001 111...110 1 lsb bipolar zero 111...111 fs/2 ?1lsb fs/2 fs = 20v 1lsb = fs/65536 figure 6. ltc1605 bipolar transfer characteristics dc performance one way of measuring the transition noise associated with a high resolution adc is to use a technique where a dc + 5 4 3 2 1 2.2 f + 2.2 f 33.2k 1% 10v input 200 ? 1% v in agnd1 ref cap agnd2 ltc1605 1605 ?f05 576k r4 50k r3 50k 5v
10 ltc1605 1605fc applicatio n s i n for m atio n wu u u signal is applied to the input of the adc and the resulting output codes are collected over a large number of conver- sions. for example in figure 7 the distribution of output code is shown for a dc input that has been digitized 10000 times. the distribution is gaussian and the rms code transition is about 1lsb. timing and control conversion start and data read are controlled by two digital inputs: cs and r/c. to start a conversion and put the sample-and-hold into the hold mode bring cs and r/c low for no less than 40ns. once initiated it cannot be restarted until the conversion is complete. converter status is indicated by the busy output and this is low while the conversion is in progress. there are two modes of operation. the first mode is shown in figure 8. the digital input r/c is used to control the start of conversion. cs is tied low. when r/c goes low the sample-and-hold goes into the hold mode and a conver- sion is started. busy goes low and stays low during the conversion and will go back high after the conversion has been completed and the internal output shift registers have been updated. r/c should remain low for no less than 40ns. during the time r/c is low the digital outputs are in a hi-z state. r/c should be brought back high within 3 s after the start of the conversion to ensure that no errors occur in the digitized result. the second mode, shown in figure 9, uses the cs signal to control the start of a conversion and the reading of the digital output. in this mode the r/c input signal should be brought low no less than 10ns before the falling edge of cs. the minimum pulse width for cs is 40ns. when cs falls, busy goes low and will stay low until the end of the conversion. busy will go high after the conversion has been completed. the new data is valid when cs is brought back low again to initiate figure 8. conversion timing with outputs enabled after conversion (cs tied low) code 0 500 1500 1000 2500 2000 4000 3500 3000 4500 count 1605 ?f07 54321012345 figure 7. histogram for 10000 conversions digital interface internal clock the adc has an internal clock that is trimmed to achieve a typical conversion time of 7 s. no external adjustments are required and, with the typical acquisition time of 1 s, throughput performance of 100ksps is assured. t 1 t 11 t 2 t 4 t 3 t 7 t 6 acquire convert convert acquire t 5 t 8 t acq t conv t 9 previous data valid previous data valid hi-z not valid hi-z data valid data valid r/c busy mode data mode 1605 ?f08
11 1605fc ltc1605 figure 11. ltc1605 nonaveraged 4096 point fft plot applicatio n s i n for m atio n wu u u acquire convert acquire data valid t 1 t 10 t 10 t 1 t 10 t 10 t 3 t 6 t 4 t conv t 12 t 7 hi-z hi-z r/c busy cs mode data bus 1605 ?f09 figure 9. using cs to control conversion and read timing frequency (khz) 130 120 100 110 ?0 ?0 ?0 ?0 ?0 0 ?0 ?0 ?0 ?0 magnitude (db) 1605 ?f11 0 5 10 15 20 25 30 35 40 45 50 f sample = 100khz f in = 1khz sinad = 87.5db thd = ?01.7db figure 10. using cs and byte to control data bus read timing t 10 t 10 t 12 t 7 t 12 hi-z hi-z hi-z hi-z high byte low byte low byte high byte r/c byte cs pins 6 to 13 pins 15 to 22 1605 ?f03
12 ltc1605 1605fc applicatio n s i n for m atio n wu u u a read. again it is recommended that both r/c and cs return high within 3 s after the start of the conversion. output data the output data can be read as a 16-bit word or it can be read as two 8-bit bytes. the format of the output data is two? complement. the digital input pin byte is used to control the two byte read. with the byte pin low the first eight msbs are output on the d15 to d8 pins and the eight lsbs are output on the d7 to d0 pins. when the byte pin is taken high the eight lsbs replace the eight msbs (figure 10). dynamic performance fft (fast fourier transform) test techniques are used to test the adc? frequency response, distortion and noise at the rated throughput. by applying a low distortion sine wave and analyzing the digital output using an fft algo- rithm, the adc? spectral content can be examined for frequencies outside the fundamental. figure 11 shows a typical ltc1605 fft plot which yields a sinad of 87.5db and thd of 102db. signal-to-noise ratio the signal-to-noise and distortion ratio (sinad) is the ratio between the rms amplitude of the fundamental input frequency to the rms amplitude of all other frequency components at the a/d output. the output is band limited to frequencies from above dc and below half the sampling frequency. figure 11 shows a typical sinad of 87.5db with a 100khz sampling rate and a 1khz input. total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency. thd is expressed as: thd = 20log v 2 2 + v 3 2 + v 4 2 ... + v n 2 v 1 where v 1 is the rms amplitude of the fundamental fre- quency and v 2 through v n are the amplitudes of the second through nth harmonics. board layout, power supplies and decoupling wire wrap boards are not recommended for high resolu- tion or high speed a/d converters. to obtain the best performance from the ltc1605, a printed circuit board is required. layout for the printed circuit board should ensure the digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital track alongside an analog signal track or underneath the adc. the analog input should be screened by agnd. figures 12 through 15 show a layout for a suggested evaluation circuit which will help obtain the best perfor- mance from the 16-bit adc. pay particular attention to the design of the analog and digital ground planes. the dgnd pin of the ltc1605 can be tied to the analog ground plane. placing the bypass capacitor as close as possible to the power supply, the reference and reference buffer output is very important. low impedance common returns for these bypass capacitors are essential to low noise opera- tion of the adc, and the foil width for these tracks should be as wide as possible. also, since any potential difference in grounds between the signal source and adc appears as an error voltage in series with the input signal, attention should be paid to reducing the ground circuit impedance as much as possible. the digital output latches and the onboard sampling clock have been placed on the digital ground plane. the two ground planes are tied together at the power supply ground connection.
13 1605fc ltc1605 applicatio n s i n for m atio n wu u u figure 12. component side silkscreen for the suggested ltc1605 evaluation circuit analog ground plane digital ground plane analog ground plane figure 14. component side showing separate analog and digital ground plane figure 13. bottom side showing analog ground plane
14 ltc1605 1605fc figure 15. ltc1605 suggested evaluation circuit schematic d15 + 3 u6a 74hc221 a b q q cext r21, 2k rcext 15 1 2 4 13 clk 1605_07d.eps d15 d14 u1 ltc1605 d13 d12 d11 c5 0.1 f r19 33.2k 1% c3 0.1 f c16 1000pf c4 2.2 f c2 2.2 f ext int v ref jp1 c17 10 f d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 6 7 8 9 10 11 12 13 15 16 17 18 19 20 21 d0 d15 d15 d14 d13 d12 d11 d10 d9 d8 2 3 4 5 6 7 8 9 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 4 r20 1k 3 u4b 74hc04 6 5 u4c 74hc04 c1 15pf 22 1 2 3 4 5 14 23 24 25 26 27 28 v in q0 u2 74hc574 19 d0 q1 18 d1 q2 17 d2 q3 16 d3 q4 15 d4 q5 14 d5 q6 13 d6 q7 12 12 u4a 74hc04 d7 1 oc 11 clk 2 7 6 5 4 3 u7 74hc160 clr load rco 15 2 3 jp3 1 ext clk int 2 3 jp5 1 v cc cs gnd enp 10 ent qd 11 d qc 12 c qb 13 b qa 14 a 2 u8 1mhz, osc out 3 gnd 1 na e2 gnd v in 7v to 15v e1 u5 lt1121 d16 mbr0520 c6 22 f 10v gnd 13 2 v in v in 4 u9 lt1019-2.5 trim 5 gnd 1 nc1 2 input 3 8 7 6 temp nc2 heater out 1 9 clk d0 d1 d2 d3 d4 d5 d6 d7 2 3 4 5 6 7 8 9 q0 u3 74hc574 19 d0 q1 18 d1 q2 17 d2 q3 16 d3 q4 15 d4 q5 14 d5 q6 13 d6 q7 12 d7 1 oc 11 clk agnd1 ref cap agnd2 dgnd byte r/c cs busy v ana v dig c8 0.1 f c7 10 f v kk v cc v kk v kk v dd v cc r16 20 c9 0.1 f c10 0.1 f digital i.c. bypassing c11 0.1 f c12 0.1 f v cc c13 0.1 f c14 0.1 f c15 10 f 2 3 jp4 1 reverse byte nornal v cc v cc v cc 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 gnd gnd clk d15 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 r8, 1.2k d8 r9, 1.2k d9 r10, 1.2k d10 r11, 1.2k d11 r12, 1.2k d12 r13, 1.2k d13 r14, 1.2k d14 r15, 1.2k r0, 1.2k d0 r1, 1.2k d1 r2, 1.2k d2 r3, 1.2k d3 r4, 1.2k d4 r5, 1.2k d5 r6, 1.2k d6 r7, 1.2k d7 jp2 led enable 10 11 u4e 74hc04 8 1 2 9 ext_clk j1 1 2 a in j2 r17 51 u4d 74hc04 r18 200 ? 1% applicatio n s i n for m atio n wu u u
15 1605fc ltc1605 package descriptio n u information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. n28 1002 .255 .015* (6.477 0.381) 1.370* (34.789) max 34 5 6 7 8 9 10 11 12 21 13 14 15 16 18 17 19 20 22 23 24 25 26 2 27 1 28 .020 (0.508) min .120 (3.048) min .130 .005 (3.302 0.127) .065 (1.651) typ .045 ?.065 (1.143 ?1.651) .018 .003 (0.457 0.076) .005 (0.127) min .008 ?.015 (0.203 ?0.381) .300 ?.325 (7.620 ?8.255) .325 +.035 ?015 +0.889 0.381 8.255 () note: 1. dimensions are inches millimeters *these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 inch (0.254mm) .100 (2.54) bsc n package 28-lead pdip (narrow 0.300 inch) (reference ltc dwg # 05-08-1510) g28 ssop 0802 0.09 ?0.25 (.0035 ?.010) 0 ?8 0.55 ?0.95 (.022 ?.037) 5.00 ?5.60** (.197 ?.221) 7.40 ?8.20 (.291 ?.323) 1234 5 6 7 8 9 10 11 12 14 13 9.90 ?10.50* (.390 ?.413) 25 26 22 21 20 19 18 17 16 15 23 24 27 28 2.0 (.079) 0.05 (.002) 0.65 (.0256) bsc 0.22 ?0.38 (.009 ?.015) millimeters (inches) dimensions do not include mold flash. mold flash shall not exceed .152mm (.006") per side dimensions do not include interlead flash. interlead flash shall not exceed .254mm (.010") per side * ** note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale 0.42 0.03 0.65 bsc 5.3 ?5.7 7.8 ?8.2 recommended solder pad layout 1.25 0.12 g package 28-lead plastic ssop (5.3mm) (reference ltc dwg # 05-08-1640)
16 ltc1605 1605fc ? linear technology corporation 2005 lt 0106 rev c ? printed in the usa package descriptio n u sw package 28-lead plastic small outline (wide 0.300 inch) (reference ltc dwg # 05-08-1620) part number description comments lt 1019-2.5 precision bandgap reference 0.05% max, 5ppm/ c max ltc1274/ltc1277 low power 12-bit, 100ksps adcs 10mw power dissipation, parallel/byte interface ltc1415 single 5v, 12-bit, 1.25msps adc 55mw power dissipation, 72db sinad ltc1419 low power 14-bit, 800ksps adc true 14-bit linearity, 81.5db sinad, 150mw dissipation lt1460-2.5 micropower precision series reference 0.075% max, 10ppm/ c max, only 130 a supply current ltc1594/ltc1598 micropower 4-/8-channel 12-bit adcs serial i/o, 3v and 5v versions related parts linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com s28 (wide) 0502 0 ?8 typ note 3 .009 ?.013 (0.229 ?0.330) .016 ?.050 (0.406 ?1.270) .291 ?.299 (7.391 ?7.595) note 4 45 .010 ?.029 (0.254 ?0.737) .037 ?.045 (0.940 ?1.143) .004 ?.012 (0.102 ?0.305) .093 ?.104 (2.362 ?2.642) .050 (1.270) bsc .014 ?.019 (0.356 ?0.482) typ note 3 .697 ?.712 (17.70 ?18.08) note 4 1 23 4 5 6 78 .394 ?.419 (10.007 ?10.643) 910 25 26 11 12 22 21 20 19 18 17 16 15 23 24 14 n/2 13 27 28 n .420 min .325 .005 recommended solder pad layout .045 .005 n 1 2 3 n/2 .050 bsc .030 .005 typ .005 (0.127) rad min inches (millimeters) note: 1. dimensions in 2. drawing not to scale 3. pin 1 ident, notch on top and cavities on the bottom of packages are the manufacturing options. the part may be supplied with or without any of the options 4. these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .006" (0.15mm)

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